This application claims the benefit of Korean Patent Application No. 2000-69234, filed on Nov. 21, 2000, the disclosures of which are incorporated by reference herein in their entirety.
1. Field of the Invention
The invention refers to a semiconductor memory device and, more particularly, to a read bitline arrangement comprising multi data read/write ports. In addition, a data read method utilizing the device is also described.
2. Description of Related Art
In general, a pair of bitlines connected to a cell of memory cell array in a semiconductor memory device reads data in reading operations and writes data in writing operations. Therefore, because the semiconductor memory device cannot perform both data reading and data writing operations simultaneously, the typical semiconductor memory device comprises unique data read/write ports in transmitting data.
On the other hand, memory devices having multiple data read and write ports provide separate read bitlines and write bitlines to read and write data and thereby permit read and write operations to be performed independently.
FIG. 1 is a block diagram illustrating an example of a conventional semiconductor memory device with multiple read ports and write ports.
The conventional semiconductor memory device of FIG. 1 includes memory cell array 10, first and second row read address decoders 12-1 and 12-2, first and second row write address decoders 14-1 and 14-2, first and second column read multiplexers 16-1 and 16-2, first and second column write multiplexers 18-1 and 18-2, and first and second column read address decoders 20-1 and 20-2. Further, the conventional semiconductor memory device of FIG. 1 also includes first and second column write address decoders 22-1 and 22-2, first and second write drivers 24-1 and 24-2, first and second data input buffers 26-1, and 26-2, and first and second data output buffers 28-1 and 28-2.
In FIG. 1, the memory cell array 10 comprises (1) multiple pairs of read bitlines rb11 and rb12, rb21 and rb22, . . . , rbk1 and rbk2, (2) multiple pairs of read word lines RWL11 and RWL12, RWL21 and RWL22, . . . , RWLm1 and RWLm2, (3) multiple pairs of write bitlines wb11 and wb12, wb21 and wb22, . . . , wbk1 and wbk2, (4) multiple pairs of write word lines WWL11 and WWL12, WWL21 and WWL22, . . . , WWLm1 and WWLm2, and a plurality of memory cells MC connected to those corresponding four types of pairs of lines.
In response to both signals applied from write word lines WWL11, WWL21, . . . , WWWm1, and write control signals wc11, wc21, . . . , wck1, each of a plurality of memory cells MC store data from each of corresponding write bitlines wb11, wb21, . . . , wbk1. In a similar way, in response to both signals applied from write word lines WWL12, WWL22, . . . , WWWm2, and write control signals wc12, wc22, . . . , wck2, each of the memory cells MC store data from each of corresponding write bitlines wb12, wb22, . . . , wbk2. Even though not illustrated in FIG. 1, write control signals wc11, wc21, . . . , wck1 are generated by buffering and delaying first column-selecting control signals WY11, WY12, . . . , WY18. Write control signals wc12, wc22, . . . , wck2 are generated by buffering and delaying second column-selecting control signals WY21, WY22, . . . , WY28.
The device of FIG. 1 includes two data read ports and two data write ports.
The functions of the blocks in the semiconductor memory device of FIG. 1 are as follows:
The first row read address decoder 12-1 decodes a first row read address FRRA, and selects one of first read word lines RWL11, RWL21, . . . , RWLm1. The second row read address decoder 12-2 decodes a second row read address SRRA and selects one of second read word lines RWL21, RWL22, . . . , RWLm2. The first row write address decoder 14-1 decodes a first row write address FRWA and selects one of first write word lines WWL11, WWL21, . . . , WWLm1. The second row write address decoder 14-2 decodes a second row write address SRWA and selects one of second write word lines WWL21, WWL22, . . . , WWLm2. The first column read multiplexer 16-1 selectively outputs data through read bitlines rb11, rb21, . . . , rbm1. In this case, when a multiplexer is a two-input type, the multiplexer selects a read data transmitted from a selected line between two adjacent read bitlines and outputs the selected read data. In a similar way, the multiplexer of a four-input type selects a read data transmitted from a selected line among four adjacent read bitlines and outputs the selected read data. Therefore, the multiplexer of an eight-input type selects a read data transmitted from a selected line among eight adjacent read bitlines and outputs the selected read data. FIG. 1 illustrates a semiconductor memory device with an eight-input multiplexer, meaning that, in response to the column-selecting control signals RY11, RY12, . . . , RY18, the multiplexer of the eight-input type selects a read data transmitted from a selected line among eight adjacent read bitlines and outputs the selected read data. The second column read multiplexer 16-2 outputs a read data selectively according to the input type of the multiplexer in the same way as the first column read multiplexer 16-1 selectively.
The first column write multiplexer 18-1 puts data to write bitlines wb11, wb21, . . . , wbm1 and the second column write multiplexer 18-2 puts data to write bitlines wb12, wb22, . . . , wbm2. In response to column-selecting control signals WY11, WY12, . . . WY18 and WY21, WY22, . . . , WY28, the first and the second column write multiplexers 18-1 and 18-2 apply the data to a selected one line of a bitline pair in a manner analogous to the read operations of the first and the second column read multiplexers 16-1 and 16-2.
The first column read address decoder 20-1 decodes three bits of the first column read address FCRA and generates eight column-selecting control signals RY11, RY12, . . . , RY18. The second column read address decoder 20-2 decodes three bits of the second column read address SCRA and generates eight column-selecting control signals RY21, RY22, . . . , RY28. The first column write address decoder 22-1 decodes three bits of the first column write address FCWA and generates eight column-selecting control signals WY11, WY12, . . . , WY18. The second column write address decoder 22-2 decodes three bits of the second column write address SCWA and generates eight column-selecting control signals WY21, WY22, . . . , WY28.
The first write driver 24-1 drives the first write data and the second write driver 24-2 drives the second write data through the write multiplexers. The first data input buffer 26-1 buffers first input data Din1 from the outside and generates a first write data. The second data input buffer 26-2 buffers second input data Din2 and generates a second write data. The first data output buffer 28-1 buffers first read data from the first column read multiplexer 16-1 and generates a first output data Dout1. The second data output buffer 28-2 buffers second read data from the second column read multiplexer 16-2 and generates a second output data Dout2.
Operations of the semiconductor memory device of FIG. 1 are as follows:
An applied write enable signal (not shown) enables a write operation and then the write operation is executed when a first write address and a first input data are applied on the rising edge of a clock signal.
An example of a write operation may be illustrated with the assumption that the first input data Din1 is xe2x80x9c00 . . . 0xe2x80x9d, the first row write address FRWA is xe2x80x9c00 . . . 0xe2x80x9d, and the first column write address FCWA is xe2x80x9c000xe2x80x9d.
The first data input buffer 26-1 buffers and outputs the first input data Din1 xe2x80x9c00 . . . 0xe2x80x9d. The first write driver 24-1 drives the output data of the first data input buffer 26-1. The first column write address decoder 22-1 decodes the first column write address FCWA as xe2x80x9c000xe2x80x9d and generates the first column-selecting control signal WY11 at logical xe2x80x9chighxe2x80x9d while the other first column-selecting control signal WY12, . . . , WY18 are in xe2x80x9clowxe2x80x9d logic levels. The first row write address decoder 14-1 decodes the first row write address FRWA as xe2x80x9c00 . . . 0xe2x80x9d and selects the first write word line WWL11 by raising it to logical xe2x80x9chighxe2x80x9d.
In response to the first column-selecting control signal WY11 being at logical xe2x80x9chighxe2x80x9d, the first column write multiplexer 18-1 outputs the data from the first data input buffer 26-1 to the adjacent eight write bitlines wb11, wb91, . . . , wb(kxe2x88x928)1 among the first write bitlines wb11, wb21, . . . , wbk1. The first column write multiplexer 18-1 also selects write control signals wc11, wc91, . . . , wc(kxe2x88x928)1 in response to the column-selecting control signal WY11 being at logical xe2x80x9chighxe2x80x9d. Then, the first write data is stored in memory cell MC connected to both the first write word line WWL11 and the adjacent eight write bitlines wb11, wb91, . . . , wb(kxe2x88x928)1.
Writing operations of the second input data Din2 are performed by the second row write address decoder 14-2, the second data input buffer 26-2, the second write driver 24-2, the second column write address decoder 22-2, and the second column write multiplexer 18-2. Each of writing operations of the first input data Din1, writing operations of the second input data Din2, reading operations of the first output data Dout1, and reading operations of the second output data Dout2 are performed independently and individually.
An applied read enable signal (not shown) initiates a read operation. The following example illustrate read operations on the assumption that the first row read address FRRA is xe2x80x9c00 . . . 1xe2x80x9d and the first column read address FCRA is xe2x80x9c001xe2x80x9d.
The first row read address decoder 12-1 decodes the first row read address FRRA as xe2x80x9c00 . . . 1xe2x80x9d and selects the first read word line RWL21, bringing it to logical xe2x80x9chighxe2x80x9d. Then, the first read data from the memory cell MC connected to the first read word line RWL21 is outputted to the first read bitlines rb11, rb21, . . . , rbk1. The first column read address decoder 20-1 decodes the first column read address FCRA as xe2x80x9c001xe2x80x9d and generates the first column-selecting signal RY12 of xe2x80x9chighxe2x80x9d logic level while the first column read address decoder 20-1 generates a xe2x80x9clowxe2x80x9d logic level in the other of the first column-selecting signals RY11, . . . , RY18. In response to the first column-selecting signal RY12 being at a xe2x80x9chighxe2x80x9d logic level, the first column read multiplexer 16-1 selects and outputs data from the adjacent eight bitlines rb21, rb101, . . . , rb(kxe2x88x927)1 from the set of first read bitlines rb11, rb21, . . . , rbk1. The first data output buffer 28-1 buffers data from the first column read multiplexer 16-1 and outputs the data through the first output data Dout1. Writing operations of the second output data Dout2 are performed by the second row read address decoder 12-2, the second column read multiplexer 16-2, the second column read address decoder 20-2, and the second data output buffer 28-2. Reading operations in the second output data Dout2, reading operations in the first output data Dout1, writing operations of the first input data Din1, and writing operations in the second input data Din2 are performed independently and individually.
However, the semiconductor memory device of FIG. 1 cannot perform both read operations and write operations in the same address simultaneously without data contention. What is needed is a device and method that can both read and write from the same address substantially simultaneously.
A Referring to FIG. 2 there is shown a circuit diagram of a typical memory cell MC that may also be utilized in the invention. The memory cell MC shown as an example in the drawing is that connected to read word lines RWL11 and RWL12, write word lines WWL11 and WWL12, read bitlines rb11 and rb12, and write bitlines wb11 and wb12.
The memory cell MC of FIG. 2 comprises NMOS transistors N1, N2, N5, N6, N7, and N8, inverter INV2, which itself comprises NMOS transistor N3 and PMOS transistor P1, and inverter INV3, which itself comprises NMOS transistor N4 and PMOS transistor P2.
Inverters INV2 and INV3 latch data between nodes Nd1 and Nd2. NMOS transistors N1 and N2 transmit read data to corresponding read bitlines rb11 and rb12 in response to selecting signals in corresponding read word lines RWL11 and RWL12, respectively. The inverter INV1 inverts the read data and transmits it to node Nd3. NMOS transistors N5 and N6 transmit write data to node Nd2 in response to selecting signals in corresponding write word lines WWL11 and WWL12, respectively. NMOS transistors N7 and N8 transmit write data of the corresponding write bitlines wb11 and wb12 to NMOS transistors N5 and N6 in response to corresponding write control signals wc11 and wc21.
As the capacity of memory cell array 10 increases, the greater are the number of memory cells are arranged in the column direction. In such case, the length of the first read bitlines rb11, rb12, . . . , rbk1, the second read bitlines rb12, rb22, . . . , rbk2, the first write bitlines wb11, wb12, . . . , wbk1, and the second write bitlines wb12, wb22, . . . , wbk2 is increased so that the number of NMOS transistors N1 and N2, N7 and N8 connected to those corresponding lines can be increased, which finally results in an increase in line load capacitances, which slows down speeds in both read and write operations, and raises the consumption voltages in the memory cells.
In addition, transmission gates transmitting read data, such as transistors N1 and N2, show good transmission performance for logical xe2x80x9clowxe2x80x9d, but poor transmission performance for logical xe2x80x9chighxe2x80x9d. A way to improve transmission performance in xe2x80x9chighxe2x80x9d logic level data is to increase both the size of NMOS transistors N1 and N2, and the size of inverter INV1. However, increasing the size of NMOS transistors N1 and N2, and the size of inverter INV1 results in increased line load capacitances.
Enlarging the sizes of the first and the second write drivers 24-1 and 24-2 can improve write speed, but at the cost of increasing line load capacitances in the first bitlines wb11, wb21, . . . , wbk1 and in the second write bitlines wb12, wb22, . . . , wbk2.
What is needed is a semiconductor memory device with improved speeds in data read/write operations regardless of increases in bitline load capacitances.
Disclosed is a semiconductor memory device comprising a memory cell array comprising a plurality of sub-arrays, said sub-arrays comprising a plurality of memory cells and repeaters, wherein each of said memory cells is connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, and wherein each of said repeaters is connected to said corresponding pair of read bitlines of each said memory cell and a corresponding pair of common main read bitlines so as to transmit read data from said corresponding pair of read bitlines to said corresponding pair of common main read bitlines in response to an applied enable control signal.
In another aspect of the invention, each said memory cell comprises a pre-determined number of read data transmission gates transmitting read data to the corresponding read bitline in response to a corresponding read word line control signal applied through the corresponding read word line, a pre-determined number of write data transmission gates transmitting write data of the corresponding write bitline in response to a corresponding write word line control signal applied through the corresponding write word line, a latch latching the write data transmitted from a pre-determined number of the write data transmission gates, and a pre-determined number of read data driving gates driving the stored data in the latch and outputting the stored data to the corresponding read data transmission gate.
In another aspect of the invention, the applied enable control signal is generated by decoding pre-determined bits in a row address.
In another aspect of the invention, each of the multiple repeaters in each sub-array according to claim 1 comprises a first inverter inverting a signal of the read bitline, a second inverter inverting the output signal of the first inverter in response to the applied enable control signal, a first PMOS transistor with a source applying a power voltage, a drain applying a signal of the read bitline, and a gate applying the output signal of the first inverter, a first NMOS transistor with a drain connected to the drain of the first PMOS transistor, and a gate applying the applied enable control signal, and a second NMOS transistor with a source applying a ground voltage, and a gate applying the output signal of the first inverter,
wherein a source of the first NMOS transistor is connected to a drain of the second NMOS transistor.
Also disclosed is a semiconductor memory device comprising a memory array comprising a plurality of sub-arrays, each said sub-array comprising a plurality of memory cells, said memory cells connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, multiple repeaters in each sub-array, each of the multiple repeaters connected to both the corresponding pair of read bitlines and the corresponding pair of common main read bitlines for connecting commonly the corresponding pair of read bitlines in each sub-array, transmitting read data in the corresponding pair of read bitlines to the corresponding pair of common main read bitlines, in response to an applied enable control signal, and multiple write repeaters in each sub-array, each of the multiple write repeaters connected to both the corresponding pair of write bitlines and the corresponding pair of common main write bitlines for connecting commonly the corresponding pair of write bitlines in each sub-array, transmitting write data in the corresponding pair of write bitlines to the corresponding pair of common main write bitlines, in response to an applied enable control signal.
In another aspect of the invention, each memory cell comprises a pre-determined number of read data transmission gates transmitting read data to the corresponding read bitline in response to a corresponding read word line control signal applied through the corresponding read word line, a pre-determined number of write data transmission gates transmitting write data of the corresponding write bitline in response to a corresponding write word line control signal applied through the corresponding write word line, a latch latching the write data transmitted from a pre-determined number of the write data transmission gates, and a pre-determined number of read data operation gates operating the stored data in the latch and outputting the stored data to the corresponding read data transmission gate.
In another aspect of the invention, the applied enable control signal is generated by decoding pre-determined bits in a row address.
In another aspect of the invention, each said repeater comprises a first inverter inverting a signal of the read bitline, a second inverter inverting the output signal of the first inverter in response to the applied enable control signal and transmitting the inverted output signal to the corresponding common main read bitline, a first PMOS transistor with a source applying a power voltage, a drain applying a signal of the read bitline, and a gate applying the output signal of the first inverter, a first NMOS transistor with a drain connected to the drain of the first PMOS transistor, and a gate applying the applied enable control signal, and a second NMOS transistor with a source applying a ground voltage, a drain connected to the source of the first NMOS transistor, and a gate applying the output signal of the first inverter.
In another aspect of the invention, each said write repeater in each said sub-array comprises a third inverter inverting a signal of the common main write bitline, a fourth inverter inverting the output of the third inverter in response to the applied enable control signal, and transmitting the inverted output signal to the write bitline, a second PMOS transistor with a source applying a power voltage, a drain applying a signal of the common main write bitline, and a gate applying the output signal of the third inverter, a third NMOS transistor with a drain connected to the drain of the second PMOS transistor, and a gate applying the applied enable control signal, a fourth NMOS transistor with a source applying a ground voltage, and a gate applying the output signal of the third inverter, and wherein a source of the third NMOS transistor is connected to a drain of the fourth NMOS transistor.
Disclosed is a data read method in a semiconductor memory device comprising a memory array comprising a plurality of sub-arrays, each said sub-array comprising a plurality of memory cells, said memory cells connected to all of a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines and a corresponding pair of write bitlines, the data read method, transmitting read data of the corresponding pair of read bitlines to a corresponding pair of common main read bitlines so as to commonly connect the corresponding pair of common main read bitlines to the corresponding pair of read bitlines in each sub-array, in response to an applied enable control signal selecting each sub-array.
In another aspect of the invention, the data read method further comprises transmitting write data in the common main write bitlines so as to commonly connect the corresponding pair of common main write bitlines in each sub-array to the corresponding pair of write bitlines, in response to an applied enable control signal in a write operation.